Custom component libraries guarantee that your PCB footprints/ symbols are exact matches for their real-part counterparts. If there is any inconsistency in pad sizes and/or spacing between pads or pin mapping during assembly, then there could be failures at assembly, poor solder joints, or total failure of the board after assembly. Make sure you create a footprint for a part using the manufacturer's data sheet & per IPC; check that the pin numbering, clearance of courtyard, & mechanical fit of the 3D model are validated before beginning the design. Create consistency in naming & version control to avoid confusion on larger projects. Taking the time to create well-validated parts saves money on re-spins & increases confidence that your designs will produce an easier, more professional & reliable process.

Automated routing produces functional layouts but generally overlooks significant design parameters, including impedances, return paths, and EMI; consequently, inefficient routing (due to the need for excessive vias) and poor signal integrity (especially where high-speed designs are concerned) will occur. Alternatively, manual routing allows complete design control over critical nets through short trace lengths, direct trace paths, and solid reference planes. Subsequently, the power and high current traces should be routed first, the sensitive signals second, and all other (lower priority) nets should be routed last. It is best to route with the same trace width and spacing using design rules as a guide. While utilizing automated routers can save time upfront, the end result from manually routing will be cleaner and make for more reliable and production-ready PCBs.

A showdown of family members' opinions.

If the ESP32 lineup were a family group chat conversation, every variant would claim to be the "most optimized." Let's break down the family drama.

ESP32-S2

A minimalist approach, the ESP32-S2 provides a single core, Wi-Fi only, no Bluetooth. The ESP32-S2 is great for secure IoT applications, provides extensive hardware security features, uses low power, and provides stability without the excess noise of additional radios.

ESP32-S3

The ESP32-S3 is the high achiever. Its dual-core design has Wi-Fi + Bluetooth LE, provides support for vector instructions for use with AI/ML applications (i.e., tiny neural networks), and is ideal for edge AI, vision and USB applications. If your project has "smart" in it, this is likely the variant that is included.

ESP32-C3 and ESP32-C6

The ESP32-C3 is the efficient underachiever. It features a RISC-V core (instead of an Xtensa core), provides low power consumption and cost-effective Wi-Fi + BLE, and is a great choice for scalable deployments of IoT where cost matters, but performance cannot be far behind.

Each ESP32-C6 represents cutting-edge technology. Both can offer RISC-V-based SoCs and both devices also include 802.11ax (Wi-Fi 6) and Bluetooth LE 5 communications standards. This variant further allows for network efficiency in busy environments. Imagine smart homes where there are multiple devices connected, but they share bandwidth (as though they were quietly talking) instead of yelling.

Key points: All are good, but fit is most important!

1.   S2: simple and secure but only has Wi-Fi capabilities
   

2.   S3: best for advanced applications with power and AI functionality
   

3.   C3: most affordable; good performance in RISC-V
   

4.   C6 :advanced connectivity (Wi-Fi 6)
   

Prior to implementing sensors, it is critical to analyze the surrounding environment prior to implementing the described sensors. To create the various types of sensor nodes, choose an ESP32-C3. If you plan to use artificial intelligence within your devices, purchase an ESP32-S3. Those that need an ideal range of connectivity options in the future will want to opt for an ESP32-C6. Lastly, if you intend for your sensor nodes to provide exemplary reliability, then configure your devices to utilize an ESP32-S2.

#mcu# #esp#

Using dual-core microcontrollers, such as the ESP32 or RP2040, allows for parallel processing by running tasks on two independent processors. By taking advantage of Core 1, for non-time-critical, processor-intensive tasks, like sensor processing, display updates or filtering algorithms, you can improve the responsiveness of time-critical tasks, such as I/O operations, networking or user interface functions.

core seperation

The main idea behind utilizing dual core microcontrollers is to separate tasks. Core 0 is responsible for all interrupt, communication stack, and other latency sensitive tasks, where as Core 1 is responsible for all non-time critical, processor intense, or blocking tasks.

This separation of tasks reduces bottlenecks from occurring, and thus aide in eliminating watchdog processor reset occurrences. On platforms such as the ESP32 (FreeRTOS based platform), tasks can be pinned to specific cores. You can do this with the API call xTaskCreatePinnedToCore() to assign a task(s) to a specific core, which will improve execution predictability, and reduce contention created by other tasks.

inter-core communication

Inter-core communication is essential. Shared Global Variables should be avoided through the use of Queues, Semaphores or Mutexes to prevent Race Conditions Always protect your shared resources with synchronization primitives to maintain the integrity of the data.

Also, minimize the dependencies between tasks on the two cores as much as possible. The more independent a task is of another, the better it will run on its designated core. For example, if you were to have a single processor do all of the pre-processing of sensor data and then only send to Core 0 the final post-processed data; this would result in less overhead (communication) between two processed sets of data.

multi-core debugging

Debugging is quite difficult on multi-core systems. Multi-core systems contain many more types of problems which make debugging more difficult than single-core systems, i.e., Dead Locks and Priority Inversion etc… As a rule, you should verify that your application is functioning prior to debugging when transferring from single to multi-core.

You also will want to monitor CPU Utilization in relation to Core 1, Core 1 may be underutilized due to Priority not being distributed evenly. Proper scheduling of processes and testing of processes should ensure the efficient utilization of all cores.

#microcontrollers#

esp32 #esp32#

When designing your PCB layout for switching power supplies, avoid introducing an excessive amount of EMI by reducing the size of the high-current loop on your board. To accomplish this, place the power supply input/output capacitors, regulator IC, inductor, and fast recovery diode as close as possible together, because short loops produce less radiated energy/noise. Additionally, while routing your traces, use short, wide traces and a solid ground plane to create low-impedance return paths for current and reduce the inductance of the loop. Also, route sensitive signals away from the switching nodes, and keep decoupling capacitors close to their respective power pins to help suppress high frequency noise. Use these layout techniques to reduce EMI and improve reliability, performance, and compliance with applicable standards such as EMC.

#PCB#

DFM will ensure that all designs created will manufacture and assemble at a reasonable cost and at a maximum of design efficiency based on available manufacturing capability. To ensure your product is within the designated manufacturer capability, it is crucial to determine what limitations exist with that specific manufacturer, (e.g., what are their drill and spacing limitations in regards to trace width), prior to finishing the design. You should also use normal tolerance and clearance settings that complement the manufacturer's capabilities when creating your part. It's also important to keep part complexity to a minimum by creating simple geometry to reduce tool operations. Also provide enough space for testing and verification of parts during assembly and inspection. Lastly, review your DFM with respect to your part's manufacturability as early as possible so that you can identify problems prior to starting production. Following these guidelines will help to improve your yield, reduce your cost, and shorten your time to market.

#PCB#

Net Classes are used to define and group specific nets together based on a common function (such as Power and/or High Speed Signals) enabling the designer to apply consistent design rules throughout the PCB layout such as Trace Width, Clearance and Layers. For example, Altium - PCB Panel > Nets > Create Net Class - allows the user to create a net class and assign all relevant nets to that particular class in order to apply rules targeted to those nets. With EasyEDA Pro, you would go to Design > Net Class Manager to create and sort your net classes and then apply them in your Design Rules. It is recommended that net classes be planned early on in the design process in any EDA tool to allow for smooth application of these design rules and to ultimately improve the manufacturability of the PCB.

Differential pairs form the basis for high-speed interfaces such as USB, Ethernet, and LVDS. To achieve this, we need to have consistent impedance and close proximity between both signals to ensure that the two signals arrive clean and at the same time.

A differential pair consists of two traces, with both traces carrying opposite and equal signals from each end of the differential pair. The distance between the two traces and their geometry determine their differential impedance (typically 90 ohm or 100 ohm). Most importantly, both traces must be identical in length, width, and environment; any variation will introduce skew and degrade the quality of the signal.

Spacing between the two traces is essential. If the traces are spaced too far apart, the differential pair will lose coupling and behave as two separate traces. If the traces are spaced too closely together, the impedance will decrease. Make sure to follow any stack-up calculations you create, and keep the spacing uniform throughout the entire route of the circuit (this is especially important through bends and layer transitions).

Speaking of bends, you should avoid using sharp corners when bending the traces; you should use either 45-degree bends or arcs when bending the traces to maintain a consistent impedance reading. You should also keep both traces together at all times; if you need to separate them or pass one trace through a detour, you will create a distortion in the signal that will also create an increase in EMI and noise.

You should always have a solid reference plane (usually GND) underneath the differential pair. Any disruption to the reference plane (e.g., splits and voids) causes the return current to take longer paths; therefore, an increase in EMI and noise will occur. When you change layers, always use a matched via for both traces and maintain the symmetry of the traces.

While it's important to match length, don't get carried away with it. There are some minor differences before the two lines meet that usually won’t cause a timing problem depending on the type of interface. I would use moderate serpentine tuning as necessary.

Finally, to limit cross-talk interference, keep your differential pairs away from other signals. An easy way to do this is to maintain a minimum of 3 times the spacing (in width) of the traces to other traces.

What's the bottom line? Differential routing is not just about drawing two traces. It is about maintaining symmetry, uniformity, and the electrical character of the path as a whole.

#PCB#

It is important to be mindful of component placement and understanding of how they will function together when designing PCBs to meet the demands of high vibration environments (automotive, Industrial & Aerospace). There are many stresses placed on the mechanical structures at the PCB level due to cyclic nature of vibrational forces. If these stresses are not properly mitigated, mechanical failure will occur within components or solder joints due to fatigue, cracks or intermittent failure.

When locating heavier components, such as inductors, large capacitors and connectors, it is best to place them as close as possible to the mounting point or areas of board support. This serves two purposes; reducing the mechanical leverage applied to the components thus reducing stress on the solder joints and keeping these heavier components from being placed in large unsupported areas of the PCB, which have the highest amount of flexure when subjected to vibration forces.

Using low-profile components whenever possible will also reduce the overall amount of inertial (force) produced during vibration for these parts. Sensitive integrated circuits (BGAs and QFNs) should be located within the mechanically stable areas of the PCB and not at the edges or corners of the PCB where bending is most pronounced.

The orientation of the components will also matter. The longer axis of the component should be aligned with the direction of the expected vibrational load. This will reduce the concentration of the stress on the solder joints. By evenly distributing the components you can avoid the imbalanced distribution of mass, which can enhance the vibrations.

For all critical areas you should reinforce these with mechanical support, such as standoffs or additional mounting holes. In addition, you may also want to utilize adhesive, underfill and/or staking compounds when securing connectors and/or larger components to provide additional mechanical stability.

Ensure your PCB thickness and stack-up are appropriate to ensure structural rigidity. Thicker pcbs or multi-layer designs will minimize flex during vibration due to increased strength. Use good soldering techniques and reliable pad design to help improve durability.

#PCB#

You can quickly get a multi-layer PCB quote using JLCPCB’s easy quoting process: upload your Gerber files to their quote page, and the system will automatically determine many parameters (such as the number of layers, board size/dimensions, thickness, and type of material used to make the boards). The system will then allow you to modify various other parameters (for example, surface finish (like ENIG), copper weight, and quantity) and see price changes in real time by updating them from the previous values automatically. Take care to define your stack-up and drill files accurately, as any mistakes could lead to being quoted incorrectly. There’s an automated design-for-manufacturability (DFM) check that will identify potential problems with your order before placing it. Both of these processes allow you to avoid having to go back and forth manually after placing your order (and receiving accurate pricing and estimated lead times in less than one minute) and receive an accurate quote for your PCBs quickly.

Take care of the edge clearance (SMT margin) when designing boards for JLC SMT assembly. If the component is placed too close to the edge of the PCB, it may get an “out of bounds” flag while being handled for panelization or on the conveyor, which may cause a non-conforming assembly. Leave at least 3 mm - 5 mm spacing from the edge of the board for normal productions and preferably more if using larger components or castellated components. If you intend to use V-cuts or mouse-bites to lower assembly costs, refrain from using them due to the possibility of breaking the solder joints by stressing them during handling. Always verify your PCB in your EDA tool’s Assembly Layer based on JLC’s Capability Guidelines before creating Gerbers for production. Proper spacing is a key element in ensuring trouble-free assembly and minimizing rework cost or likelihood of non-conforming parts.

The JLC X-ray inspection provides verification for the solder joint integrity of hidden solder joints (especially on BGAs and QFNs). Key items to review on JLC X-ray reports are ball alignment, void percentage, and bridges between the pads. Voids should typically be less than ~25% to provide an acceptable level of reliability in most uses. Verify the even distribution of solder and proper wetting across all joints. Issues with alignment or excessive amounts of voiding may indicate issues with the solder paste reflow profile or stencil. Additionally, verify that all expected solder joints are accounted for, as missing solder joint connections can happen through not enough solder paste. X-ray is used in conjunction with AOI; therefore, you should check both prior to issuing acceptance of a board. Identifying issues at this early stage helps avoid expensive failure in the field.

The part looked simple: a small bracket with straightforward geometry and a clear function.

But when final assembly began, the issue appeared.
Tool access was tighter than expected, installation space was limited, and the mounting sequence became less convenient than it seemed in the model.

Nothing was dramatically wrong with the part itself.
The challenge came from how the part behaved in the real assembly environment.

This is a common reminder in sheet metal development:
a part can look simple in CAD and still become a bottleneck at the final stage.

#SheetMetal# #Assembly# #MechanicalDesign# #Manufacturing# #BracketDesign# #ProductDevelopment

Many cost increases do not come from the overall part size.

They come from specific details.

Sometimes it’s:

• an unnecessarily tight tolerance
• a difficult feature position
• too many secondary operations
• a finish requirement added late
• complex hardware insertion needs
• packaging or protection requirements that were overlooked

These things may seem minor at first, but they can significantly affect manufacturing cost and lead time.

What part detail has caused the biggest unexpected cost increase in your experience?

This could be a useful discussion for engineers trying to design more cost-aware parts from the start.

#SheetMetal ##CostOptimization# #Manufacturing# #Engineering# #DesignForCost# #HardwareDesign# #Production#

In some sheet metal projects, the best structural choice is not always the best visual choice.

For example:

• a stronger feature may affect external appearance
• a more practical bend may change the product style
• visible fasteners may be easier to assemble
• a cleaner surface may require more process control

This balance shows up often in enclosures, consumer-facing hardware, and branded equipment.

So here's the question:

When appearance and function conflict in a sheet metal part, which one usually wins in your project — and why?

It would be great to hear how different teams make that decision.

#sheetmetal# #surfacefinish#

Surface finishing is often treated as a default step—but in some cases, it can actually cause more problems than it solves.

Here are situations where skipping finishing might be the better choice:

🔹 Tight Tolerance Assemblies

Coatings like powder coating or anodizing add thickness.

Even a small buildup can affect fit, alignment, or clearance.

👉 Raw parts may ensure better precision in critical fits

🔹 Electrical Contact Surfaces

Some finishes (like standard anodizing) reduce conductivity.

👉 For grounding or electrical interfaces, raw metal or conductive finishes are often preferred

🔹 Cost-Sensitive Prototypes

Surface finishing adds both cost and lead time.

👉 For early-stage testing, raw parts are often enough

🔹 Hidden/Internal Components

If the part isn't visible or exposed to harsh environments, finishing may not add real value

🔹 Post-Processing Required

If parts need additional machining, tapping, or welding after fabrication:

• Coating may get damaged
• Extra steps may be needed

💬Discussion:

Have you ever skipped surface finishing intentionally?

What was your deciding factor—cost, function, or assembly?

#sheetmetal#

#surfacefinish#

Surface finishing isn't just about appearance—it affects durability, conductivity, corrosion resistance, and even assembly fit.

Here's a quick breakdown of common sheet metal finishes:

🔹 No Finish (Raw)

• Lowest cost, fastest turnaround
• Keeps original material properties
• May oxidize or scratch easily

👉 Best for internal parts or quick prototypes

🔹 Brushing

• Creates a uniform, textured surface
• Improves visual consistency
• Does not provide strong corrosion protection

👉 Often used for aesthetic aluminum or stainless parts

🔹 Powder Coating

• Thick protective layer
• Excellent corrosion resistance
• Wide range of colors
• Adds thickness (important for tight fits)

👉 Great for enclosures and outdoor applications

🔹 Anodizing (Aluminum)

• Improves corrosion resistance
• Creates clean, premium look
• Maintains relatively tight tolerances

👉 Common for consumer-facing aluminum parts

🔹 Hardcoat Anodizing

• Much thicker and harder than standard anodizing
• High wear resistance
• Slight dimensional change

👉 Used in high-friction or industrial environments

🔹 Conductive Anodizing

• Maintains electrical conductivity
• Provides light corrosion protection

👉 Ideal for electronic housings and grounding applications

🔹 Silkscreen

• Used for logos, labels, markings
• Typically applied after coating or anodizing

👉 Great for branding and instructions

🔹 Laser Marking

• Permanent, high-precision marking
• No added thickness
• Very durable

👉 Used for serial numbers, QR codes, branding

💬 Discussion:

When choosing surface finishes, what matters most in your projects—appearance, durability, or functionality?
Have you ever had issues with coating thickness or finish affecting assembly?

#sheetmetal# #surfacefinish#

PCB trace close-up (conceptualized)

Signals, in PCB design, are not instantaneously transmitted, but rather propagate as electromagnetic waves over copper traces, which is fundamental to understanding why trace-length can be critical to signal integrity.

The speed at which a signal propagates depends on the material in which the signal is propagating, with typical standards for FR-4 PCB materials being approximately 50-70% of the speed of light. Thus, a signal propagating from one PCB pad to another may take 100 + picoseconds to travel a nominal distance of 2-3 centimeters. This travel time is relatively significant when compared with the fast rising (edge rate) of the signal itself.

High-density PCB routing

In addition to the delay of a signal traveling on its forward path, the signals also have a return path back to the source, typically by way of a common ground. Increased trace lengths create larger return loops, therefore increasing the inductance and the effects of voltage/potential noise from any external electromagnetic interference (EMI) sources.

Higher trace lengths increase resistive/capacitive characteristics, which in turn may attenuate the signal, create longer rising/falling signals, and create potential distortion. When considered at higher frequencies, traces can behave like transmission lines, where impedance mismatching effects create reflections. Reflections can introduce ringing, as well as logic errors.

Timing is another major consideration. When considering buses or high-speed interfaces, a difference in trace length will cause some skew (i.e., signal arriving at different times). This will potentially cause the system to lose its intended relationship of synchronization for such devices as memory or differentials.

The reason designers apply techniques such as length matching, controlled impedance routing, and appropriate terminations is because keeping traces as short, direct, and grounded to the reference plane will help to maintain the integrity of the signal.

PCB with short, direct, and grounded traces

Takeaway? Trace length is not simply an attribute of geometry; it impacts the manner in which the signal behaves. As speeds continue to increase, propagation management is critical to reliable and predictable circuit operation.

When designing printed circuit boards (PCBs), "high speed" is not solely determined by clock frequency, but rather by the rate at which signals are switching (rise and fall times). When rise/fall times are down to the point where they are close to the speed it takes to propagate a signal along a trace, layout becomes very important; as a rule of thumb, when the length of a trace exceeds approximately 1/10th of its effective wavelength (also called edge length), it must be treated as if it were a transmission line. At that point, reflection, impedance mismatch, and ringing will create distorted signals.

PCB close-up

This is why "slow" systems (e.g., tens of MHz) may require fast design techniques if they incorporate very fast digital logic families with very sharp edges.

Three layout considerations are particularly important for high-speed circuit designs; controlled impedance (all traces and cables have impedance), continuous ground plane (a common reference with low impedance), and tightly coupled return path (the return current flow follows the path of least impedance; in most cases directly under the trace). In high-speed applications, signals form loops, and return current finds the path of least impedance, typically directly under the trace. Interruptions (such as ground splits) will increase the total area of the loop and increase the amount of electromagnetic interference (EMI).

Dense PCB routing / high-speed layout

When designing for fast applications, crosstalk must also be taken into account. Two close traces that run parallel and adjacent to each other can couple energy to one another over long cable lengths. Proper trace spacing and layer management will help reduce the amount of crosstalk present in a design.

PCB layer management can be an important factor to consider

Interface Standards are another triggering mechanism. Controlled routing (i.e., differential routing methods) and matched lengths are required of signal traces regardless of clock rate for Protocols such as USB, Ethernet and DDR memory.

The takeaway from this is that the phrase "High Speed" is defined as beginning at the point where physics (not simply connectivity) starts to govern signal behavior. Therefore, if you have fast edge rates, long trace lengths, or tight timing constraints on your signals, layout is critical for successful operation.

E-Ink Display

E-Ink displays are an excellent choice for low-energy IoT dashboard systems because they only draw power when being updated. Unlike LCD screens which require a constant supply of power to maintain an image, E-Ink displays retain an image without needing any power applied. Therefore, they are a great fit for battery operated systems that require data to be updated from time to time.

This characteristic makes E-Ink displays well-suited for applications such as sensors, status information, and remote monitoring devices that don't update often. When combined with low power microcontrollers, E-Ink displays can endure for months or years with small batteries.

E-Ink displays have lower refresh rates and only have limited colors. So, they are best for displaying static or slowly changing data.

The end result is ultra-low power visualisation while retaining readability, even in bright conditions.